SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same

ABSTRACT

An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of fabricating asemiconductor device, and more particularly, to a method of fabricatinga body contact of a silicon on insulator metal oxide semiconductor fieldeffect transistor (hereinafter, referred to as “SOI MOSFET”).

[0003] 2. Description of the Related Art

[0004] Body contacts are intended to prevent the floating body effect ina transistor. The floating body effect is a phenomenon in which thethreshold voltage of the transistor varies because the body of thetransistor does not have a certain fixed voltage value during operation.The floating body effect is particularly important in MOS analogtechniques. A node having a predetermined direct current (DC) voltage isconnected to the body of a transistor when designing MOS analog circuitsin order to prevent the floating body effect. The low voltage source orthe high voltage source of a chip is connected to the body of atransistor depending on the type (p⁻ type or n⁻ type) of the body in adigital circuit. Even in the case of SOI MOSFETs, bodies of transistorshave predetermined voltages applied so that the body floating effectdoes not occur.

[0005] Hereinafter, the prior art will be described with reference tothe attached drawings. Like reference numerals in the drawings denotethe same features in the drawings.

[0006]FIG. 1 is a plan view of a SOI MOSFET having a body contactaccording to a conventional trench method. Referring to FIG. 1, the SOIMOSFET includes an external trench isolation ring 11, a body powersupply ring 12 having a p⁺ (p plus) region, a partial trench isolationring 13 isolated from a peripheral active region, an active region 14,e.g., a drain of a transistor, an active region 15, e.g., a source ofthe transistor, a gate 16 between the drain and the source, a contactwindow 17 contacting the power supply ring 12, and a peripheral activeregion 19.

[0007]FIG. 2 is a cross-sectional view of the SOI MOSFET shown in FIG. 1taken along line X-X. FIG. 2 shows a p⁻ type semiconductor substrate 20,a buried oxide layer 21 on the p⁻ type semiconductor substrate 20, p⁻type bodies 14 and 15 on the buried oxide layer 21, a partial trenchisolation ring 13 around the p⁻ type bodies 14 and 15, a p⁺ body powersupply ring 12 next to the partial trench isolation ring 13, an externaltrench isolation ring 11 next to the p⁺ body power supply ring 12, agate oxide layer 18 on the p⁻ bodies 14 and 15, a gate 16 on the gateoxide layer 18, and a peripheral active region 19.

[0008]FIG. 3 is a cross-sectional view of the SOI MOSFET shown in FIG. 1taken along line Y-Y. FIG. 3 shows a p⁻ type semiconductor substrate 20,a buried oxide layer 21 on the p⁻ type semiconductor substrate 20, adrain 14 and a source 15 on the buried oxide layer 21, a gate 16 betweenthe drain 14 and the source 15, a gate oxide layer 18 underneath thegate 16, a partial trench isolation ring 13 around the drain 14 and thesource 15, a body power supply ring 12, which is next to the partialtrench isolation ring 13, for supplying power to a body, i.e., a p⁺region, an external trench isolation ring 11, and a p⁻ region 22underneath the partial trench isolation ring 13.

[0009] Stray capacitance exists at contacts 100 and 110 between the p⁺region, i.e., the body contact 12, and the p⁻ region, i.e., the bodies14 and 15 of the transistor in the SOI MOSFET shown in FIGS. 1, 2, and3. Stray capacitance can limit the performance of the transistor,especially, the operating speed and frequency of a circuit. It is noteasy to form a metal interconnection line which needs a wide area inview of the layout when a voltage, e.g., ground voltage, must be appliedto a body.

SUMMARY OF THE INVENTION

[0010] To solve the above problems, it is an object of the presentinvention to provide an SOI MOSFET that can reduce a floating bodyeffect without stray capacitance at a contact and an additional metalinterconnection line supplying power to the contact.

[0011] It is another object of the present invention to provide a methodfabricating the same.

[0012] Accordingly, to achieve the above first object, there is provideda silicon-on-insulator metal oxide semiconductor field effect transistor(SOI MOSFET). The SOI MOSFET includes a semiconductor substrate, aburied oxide layer, a body, a gate oxide layer, a gate, and a bodycontact. The semiconductor substrate can be a semiconductor wafer. Theburied oxide layer is an oxide layer which is formed on thesemiconductor substrate. The body is an active region of a transistorwhich is formed on the buried oxide layer. The gate oxide layer isformed on the body, and the gate is formed on the gate oxide layer. Thebody contact supplies power to the body to prevent a floating bodyeffect. The body contact is formed by forming a trench perforating anisolation region surrounding the body, the body, and the buried oxidelayer and then filling the trench with a conductive material so that thebody is electrically connected to the semiconductor substrate.

[0013] The conductive material can be formed of one of a metal layer, atungsten layer, a silicon epitaxial layer and a combination of at leasttwo of the above layers. The gate can be formed of metal or polysilicon

[0014] The SOI MOSFET further includes a region into which predeterminedimpurity ions are implanted and generated on the semiconductor substratein contact with the lower portion of the body contact so that an ohmiccontact is formed between the body contact and the semiconductorsubstrate.

[0015] In one embodiment, the trench narrows as the trench deepens.Alternatively, the trench narrows in a step-wise manner as the trenchdeepens. In accordance with the invention, there is also provided amethod of fabricating a SOI MOSFET. In the method, a buried oxide layeris formed on a semiconductor substrate. A silicon body is formed on theburied oxide layer. The silicon body is defined as a channel region, abody contact, an isolation region, a field oxide layer region, aperipheral region, and the isolation region and the field oxide layerare etched. The isolation region is further etched until the buriedoxide layer is exposed. Oxide layers are formed in the isolation regionand the field oxide layer region. A gate oxide layer is formed on apredetermined region on the body and a gate is formed on the gate oxidelayer. The semiconductor substrate is etched from an upper part toward alower part so that the body and the buried oxide layer are perforated toform a trench. Predetermined impurity ions are implanted into apredetermined region of the semiconductor substrate to form an ohmiccontact. The trench is filled with a conductive material.

[0016] In one embodiment, the predetermined region of the semiconductorsubstrate into which the impurity ions are implanted is the bottom ofthe trench.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings in which like reference characters refer tothe same parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention.

[0018]FIG. 1 is a plan view of a SOI MOSFET having a body contactaccording to a conventional trench method.

[0019]FIG. 2 is a cross-sectional view taken along line X-X of the SOIMOSFET shown in FIG. 1.

[0020]FIG. 3 is a cross-sectional view taken along line Y-Y of the SOIMOSFET shown in FIG. 1.

[0021]FIG. 4 is a plan view of a SOI MOSFET having a body contactaccording to an embodiment of the present invention.

[0022]FIG. 5 is a cross-sectional view taken along line X-X of the SOIMOSFET shown in FIG. 4.

[0023]FIGS. 6 through 9 are cross-sectional views showing steps offabricating the SOI MOSFET shown in FIGS. 4 and 5 according to thepresent invention.

[0024]FIG. 10 shows a trench having an inverted trapezoid shape.

[0025]FIG. 11 shows a trench having a step shape.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026]FIG. 4 is a plan view of a SOI MOSFET having a body contactaccording to one embodiment of the present invention, and FIG. 5 is across-sectional view taken along line X-X of the SOI MOSFET shown inFIG. 4. Referring to FIGS. 4 and 5, the SOI MOSFET according to thepresent invention includes a gate 46, a source 45, a drain 44, isolationregions 41, a p⁻ body 440, a field oxide layer region 441, and a bodycontact 442. Here, the body contact 442 is formed in the field oxidelayer region 441 to directly connect a body divided into the source 45and the drain 44 to a p⁻ semiconductor substrate 50. A peripheral activeregion 49 is an active region.

[0027]FIG. 5 shows a p⁻ semiconductor substrate 50, a buried oxide layer51 on the p semiconductor substrate 50, a p⁻ body 440 on the buriedoxide layer 51, isolation regions 41 next to the p⁻ body 440, a gateoxide layer 48 on the p⁻ body 440, a gate 46 on the gate oxide layer 48,a field oxide layer region 441 on one side of the p⁻ body 440, a bodycontact 442 contacting the field oxide layer region 441, a p⁺ region 443into which impurity ions are implanted to form an ohmic contact when thep⁻ body 440 connects to the p⁻ semiconductor substrate 50, a metal 446with which the body contact 442 is doped, and tungsten 444 on the metal446.

[0028] Here, a region 445 is a contact which connects the p⁻ body 440 tothe p+region 443. A peripheral active region 49 is an external activeregion.

[0029] Referring to FIGS. 4 and 5, in the SOI MOSFET according to thepresent invention, power for the semiconductor substrate 50 is suppliedto the p⁻ body 440 through the body contact 442, which is filled withmaterials, i.e., tungsten 444 and a metal 446, having high electricalconductivity. Thus, there is no need to use an additional metal line toprevent a floating body effect of the p⁻ body 440. Also, straycapacitance does not occur in region 445. In order to prevent thefloating body effect, the body contact 442 has an area smaller than ametal line. Thus, the chip size is reduced.

[0030]FIGS. 6 through 9 are cross-sectional views showing steps offabricating the SOI MOSFET shown in FIGS. 4 and 5 according to anembodiment of the present invention. Referring to FIG. 6, a buried oxidelayer 51 and a silicon body 52 are formed on a semiconductor substrate50.

[0031] With reference to FIG. 7, a trench mask layer 53 is formed on thesilicon body 52 and a photoresist (not shown) is deposited on the trenchmask layer 53. The silicon body 52 is etched to form isolation regions41, a p⁻ body or channel region 440, a field oxide layer region 441, abody contact 442, and a peripheral active region 49 using thephotoresist as a mask. Here, the isolation regions 41 and the fieldoxide layer region 441 are etched to predetermined depths. The trenchmask layer 53 may be a pad oxide layer, a pad nitride layer, or a hardmask layer.

[0032] Referring to FIG. 8, the isolation regions 41 are etched to theburied oxide layer 51. Here, a photoresist 54 is deposited to protectother regions from being etched.

[0033] With reference to FIG. 9, oxide layers (regions indicated byslanted lines) are formed in the isolation regions 41 and the fieldoxide layer 441. A gate oxide layer 48 and a gate 46 are sequentiallyformed on the channel region 440 and on portions of the oxide layersformed in the isolation regions 41 and the field oxide layer region 441in contact with both sides of the channel region 440.

[0034] Here, the oxide layers (regions indicated by slanted lines) arepreferably made by chemical vapor deposition (CVD). The oxide layers arecompleted by a planarization process, such as etch back or chemicalmechanical polishing. The gate oxide layer 48 is a thermal oxide layer.

[0035] The gate 46 is preferably a stack of a conductive layer (notshown) and a capping insulator (not shown). However, the gate 46 may bea conductive layer only. The conductive layer is formed of polysiliconor metal, and the capping insulator is formed of CVD oxide or siliconnitride made by CVD.

[0036] Referring to FIG. 9, an oxide layer 55 is formed on an entirewafer surface. A trench is formed from the body contact 442 to thesemiconductor substrate 50, and then predetermined impurity ions areimplanted into a predetermined region of the substrate, i.e., the bottomof the trench, thereby forming an ohmic region 60. The oxide layer 55serves as a buffer and relieves stress in the ion implantation process.

[0037] The trench is filled with conductive materials on which an oxidelayer 57 is formed. The conductive materials are preferably formed ofmetal, tungsten, a silicon epitaxial layer, and a combination of atleast two of these.

[0038]FIG. 10 shows a trench having an inverted trapezoid shape.Referring to FIG. 10, the trench narrows as it deepens, therebypreventing voids between the conductive materials and the oxide layer 57formed on the conductive materials.

[0039]FIG. 11 shows a trench having a step shape. Referring to FIG. 11,as the trench deepens, it narrows in a step-wise manner, therebypreventing voids between the conductive materials and the oxide layer 57formed on the conductive materials. A first trench is formed to apredetermined depth, and then a second trench smaller than the firsttrench is formed underneath the first trench.

[0040] As described above, in the SOI MOSFET according to the presentinvention, an additional metal interconnection line for supplying a bodywith power is not needed. Thus, used area is reduced and the malfunctionof a circuit due to stray capacitance of a contact is prevented.

[0041] While this invention has been particularly shown and describedwith references to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the following claims.

1. A silicon-on-insulator metal oxide semiconductor field effecttransistor (SOI MOSFET) comprising: a semiconductor substrate; a buriedoxide layer formed on the semiconductor substrate; a body on the buriedoxide layer, the body being an active region of a transistor; a gateoxide layer formed on the body; a gate formed on the gate oxide layer;and a body contact supplying power to the body, wherein the body contactis formed by forming a trench perforating an isolation region, the body,and the buried oxide layer and filling the trench with a conductivematerial so that the body is electrically connected to the semiconductorsubstrate.
 2. The SOI MOSFET of claim 1, wherein the gate is formed ofat least one of metal and polysilicon.
 3. The SOI MOSFET of claim 1,wherein the conductive material is formed of one of a metal layer, atungsten layer, a silicon epitaxial layer, and a combination layer of atleast two of a metal layer, a tungsten layer and a silicon epitaxiallayer.
 4. The SOI MOSFET of claim 1, further comprising a region intowhich predetermined impurity ions are implanted and generated on thesemiconductor substrate in contact with the lower portion of the bodycontact so that an ohmic contact is formed between the body contact andthe semiconductor substrate.
 5. The SOI MOSFET of claim 1, wherein thetrench narrows as the trench deepens.
 6. The SOI MOSFET of claim 5,wherein the trench narrows in a stepwise manner as the trench deepens.7. A method of fabricating a SOI MOSFET comprising: forming a buriedoxide layer on a semiconductor substrate; forming a silicon body on theburied oxide layer; defining the silicon body as a channel region, abody contact, an isolation region, a field oxide layer region, aperipheral active region and etching the isolation region and the fieldoxide layer; further etching the isolation region until the buried oxidelayer is exposed; forming oxide layers in the isolation region and thefield oxide layer region; forming a gate oxide layer on a predeterminedregion on the body and forming a gate on the gate oxide layer; etchingthe semiconductor substrate from an upper part toward a lower part sothat the body and the buried oxide layer are perforated to form atrench; implanting predetermined impurity ions into a predeterminedregion of the semiconductor substrate to form an ohmic contact; andfilling the trench with a conductive material.
 8. The method of claim 7,wherein the predetermined region of the semiconductor substrate is thebottom of the trench.